Generally, to program a multi-level cell (MLC) flash memory device, program and program verify operations are needed. A program verify operation may include an address decode operation, a sensing operation, and a data resolving operation. In a conventional MLC program verify sensing operation, data is generated by an address transition detector (ATD) circuit. The data gets latched by the output of a sense amplifier, which generates the control signal for the latching operation. The data generated by the ATD is latched when the sense amplifier changes state.
The output of the sense amplifier is set to a pre-determined state at the beginning of the sense operation. When the sense amplifier changes state, indicating that the data generated by ATD needs to be latched, the sense amplifier signal is transmitted on a metal line through the entire flash memory array to a peripheral latch logic. The sense amplifier control signal transmitted to the peripheral latch logic will be termed “VBUS” herein. VBUS latches the data present at the input of the latch logic, and passes it to output buffers.
Since a single VBUS signal is shared between sense amplifiers in every partition and is routed through the core, the signal path is very long and also narrow. If a sense amplifier nearest the peripheral latch logic trips, the VBUS has less resistance and capacitance in the path, and latches the data with minimum delay. A sense amplifier farther from the peripheral latch logic will take a longer time to transmit VBUS from the sense amplifier to the peripheral latch logic. If the variance in ramp times of VBUS is not accurately matched with the data being generated by ATD, it is possible to latch incorrect data during the program verify operation.
In a conventional MLC program verify scheme, a fixed time interval 108 is allocated to every sense outcome after modeling the VBUS path 102, as illustrated in FIG. 1. ATD generates an incoming data stream 104 used to latch three possible outcomes, (11, 10, 00). The outcomes are equally spaced in time. However, the VBUS response 106 will change based on supply voltage, temperature, and process, while the ATD response is supply voltage and process independent. Thus, in some cases when a fast verify operation is initiated, incorrect data could be latched, forcing the usage of a slow verify operation which in turn impacts overall program performance.